; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s

target triple = "aarch64-unknown-linux-gnu"

;
; FCVT H -> S; Without load instr
;

define void @fcvt_v2f16_to_v2f32(<2 x half> %a, ptr %b) #0 {
; CHECK-LABEL: fcvt_v2f16_to_v2f32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
; CHECK-NEXT:    ptrue p0.s, vl4
; CHECK-NEXT:    uunpklo z0.s, z0.h
; CHECK-NEXT:    fcvt z0.s, p0/m, z0.h
; CHECK-NEXT:    str d0, [x0]
; CHECK-NEXT:    ret
  %res = fpext <2 x half> %a to <2 x float>
  store <2 x float> %res, ptr %b
  ret void
}

define void @fcvt_v4f16_to_v4f32(<4 x half> %a, ptr %b) #0 {
; CHECK-LABEL: fcvt_v4f16_to_v4f32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
; CHECK-NEXT:    ptrue p0.s, vl4
; CHECK-NEXT:    uunpklo z0.s, z0.h
; CHECK-NEXT:    fcvt z0.s, p0/m, z0.h
; CHECK-NEXT:    str q0, [x0]
; CHECK-NEXT:    ret
  %res = fpext <4 x half> %a to <4 x float>
  store <4 x float> %res, ptr %b
  ret void
}

define void @fcvt_v8f16_to_v8f32(<8 x half> %a, ptr %b) #0 {
; CHECK-LABEL: fcvt_v8f16_to_v8f32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
; CHECK-NEXT:    uunpklo z1.s, z0.h
; CHECK-NEXT:    ptrue p0.s, vl4
; CHECK-NEXT:    ext z0.b, z0.b, z0.b, #8
; CHECK-NEXT:    fcvt z1.s, p0/m, z1.h
; CHECK-NEXT:    uunpklo z0.s, z0.h
; CHECK-NEXT:    fcvt z0.s, p0/m, z0.h
; CHECK-NEXT:    stp q1, q0, [x0]
; CHECK-NEXT:    ret
  %res = fpext <8 x half> %a to <8 x float>
  store <8 x float> %res, ptr %b
  ret void
}

define void @fcvt_v16f16_to_v16f32(<16 x half> %a, ptr %b) #0 {
; CHECK-LABEL: fcvt_v16f16_to_v16f32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    // kill: def $q1 killed $q1 def $z1
; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
; CHECK-NEXT:    uunpklo z2.s, z1.h
; CHECK-NEXT:    uunpklo z3.s, z0.h
; CHECK-NEXT:    ext z1.b, z1.b, z1.b, #8
; CHECK-NEXT:    ext z0.b, z0.b, z0.b, #8
; CHECK-NEXT:    ptrue p0.s, vl4
; CHECK-NEXT:    uunpklo z1.s, z1.h
; CHECK-NEXT:    uunpklo z0.s, z0.h
; CHECK-NEXT:    fcvt z1.s, p0/m, z1.h
; CHECK-NEXT:    fcvt z2.s, p0/m, z2.h
; CHECK-NEXT:    fcvt z0.s, p0/m, z0.h
; CHECK-NEXT:    stp q2, q1, [x0, #32]
; CHECK-NEXT:    movprfx z1, z3
; CHECK-NEXT:    fcvt z1.s, p0/m, z3.h
; CHECK-NEXT:    stp q1, q0, [x0]
; CHECK-NEXT:    ret
  %res = fpext <16 x half> %a to <16 x float>
  store <16 x float> %res, ptr %b
  ret void
}

;
;
; FCVT H -> S
;

define void @fcvt_v2f16_v2f32(ptr %a, ptr %b) #0 {
; CHECK-LABEL: fcvt_v2f16_v2f32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ptrue p0.s, vl2
; CHECK-NEXT:    ld1h { z0.s }, p0/z, [x0]
; CHECK-NEXT:    fcvt z0.s, p0/m, z0.h
; CHECK-NEXT:    str d0, [x1]
; CHECK-NEXT:    ret
  %op1 = load <2 x half>, ptr %a
  %res = fpext <2 x half> %op1 to <2 x float>
  store <2 x float> %res, ptr %b
  ret void
}

define void @fcvt_v4f16_v4f32(ptr %a, ptr %b) #0 {
; CHECK-LABEL: fcvt_v4f16_v4f32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ptrue p0.s, vl4
; CHECK-NEXT:    ld1h { z0.s }, p0/z, [x0]
; CHECK-NEXT:    fcvt z0.s, p0/m, z0.h
; CHECK-NEXT:    str q0, [x1]
; CHECK-NEXT:    ret
  %op1 = load <4 x half>, ptr %a
  %res = fpext <4 x half> %op1 to <4 x float>
  store <4 x float> %res, ptr %b
  ret void
}

define void @fcvt_v8f16_v8f32(ptr %a, ptr %b) #0 {
; CHECK-LABEL: fcvt_v8f16_v8f32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mov x8, #4
; CHECK-NEXT:    ptrue p0.s, vl4
; CHECK-NEXT:    ld1h { z0.s }, p0/z, [x0, x8, lsl #1]
; CHECK-NEXT:    ld1h { z1.s }, p0/z, [x0]
; CHECK-NEXT:    fcvt z0.s, p0/m, z0.h
; CHECK-NEXT:    fcvt z1.s, p0/m, z1.h
; CHECK-NEXT:    stp q1, q0, [x1]
; CHECK-NEXT:    ret
  %op1 = load <8 x half>, ptr %a
  %res = fpext <8 x half> %op1 to <8 x float>
  store <8 x float> %res, ptr %b
  ret void
}

define void @fcvt_v16f16_v16f32(ptr %a, ptr %b) #0 {
; CHECK-LABEL: fcvt_v16f16_v16f32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mov x8, #8
; CHECK-NEXT:    mov x9, #12
; CHECK-NEXT:    ptrue p0.s, vl4
; CHECK-NEXT:    mov x10, #4
; CHECK-NEXT:    ld1h { z0.s }, p0/z, [x0, x8, lsl #1]
; CHECK-NEXT:    ld1h { z1.s }, p0/z, [x0, x9, lsl #1]
; CHECK-NEXT:    ld1h { z2.s }, p0/z, [x0, x10, lsl #1]
; CHECK-NEXT:    ld1h { z3.s }, p0/z, [x0]
; CHECK-NEXT:    fcvt z0.s, p0/m, z0.h
; CHECK-NEXT:    fcvt z1.s, p0/m, z1.h
; CHECK-NEXT:    stp q0, q1, [x1, #32]
; CHECK-NEXT:    movprfx z0, z3
; CHECK-NEXT:    fcvt z0.s, p0/m, z3.h
; CHECK-NEXT:    movprfx z1, z2
; CHECK-NEXT:    fcvt z1.s, p0/m, z2.h
; CHECK-NEXT:    stp q0, q1, [x1]
; CHECK-NEXT:    ret
  %op1 = load <16 x half>, ptr %a
  %res = fpext <16 x half> %op1 to <16 x float>
  store <16 x float> %res, ptr %b
  ret void
}

;
; FCVT H -> D
;

define void @fcvt_v1f16_v1f64(ptr %a, ptr %b) #0 {
; CHECK-LABEL: fcvt_v1f16_v1f64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr h0, [x0]
; CHECK-NEXT:    fcvt d0, h0
; CHECK-NEXT:    str d0, [x1]
; CHECK-NEXT:    ret
  %op1 = load <1 x half>, ptr %a
  %res = fpext <1 x half> %op1 to <1 x double>
  store <1 x double> %res, ptr %b
  ret void
}

define void @fcvt_v2f16_v2f64(ptr %a, ptr %b) #0 {
; CHECK-LABEL: fcvt_v2f16_v2f64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ptrue p0.d, vl2
; CHECK-NEXT:    ld1h { z0.d }, p0/z, [x0]
; CHECK-NEXT:    fcvt z0.d, p0/m, z0.h
; CHECK-NEXT:    str q0, [x1]
; CHECK-NEXT:    ret
  %op1 = load <2 x half>, ptr %a
  %res = fpext <2 x half> %op1 to <2 x double>
  store <2 x double> %res, ptr %b
  ret void
}

define void @fcvt_v4f16_v4f64(ptr %a, ptr %b) #0 {
; CHECK-LABEL: fcvt_v4f16_v4f64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mov x8, #2
; CHECK-NEXT:    ptrue p0.d, vl2
; CHECK-NEXT:    ld1h { z0.d }, p0/z, [x0, x8, lsl #1]
; CHECK-NEXT:    ld1h { z1.d }, p0/z, [x0]
; CHECK-NEXT:    fcvt z0.d, p0/m, z0.h
; CHECK-NEXT:    fcvt z1.d, p0/m, z1.h
; CHECK-NEXT:    stp q1, q0, [x1]
; CHECK-NEXT:    ret
  %op1 = load <4 x half>, ptr %a
  %res = fpext <4 x half> %op1 to <4 x double>
  store <4 x double> %res, ptr %b
  ret void
}

define void @fcvt_v8f16_v8f64(ptr %a, ptr %b) #0 {
; CHECK-LABEL: fcvt_v8f16_v8f64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mov x8, #4
; CHECK-NEXT:    mov x9, #6
; CHECK-NEXT:    ptrue p0.d, vl2
; CHECK-NEXT:    mov x10, #2
; CHECK-NEXT:    ld1h { z0.d }, p0/z, [x0, x8, lsl #1]
; CHECK-NEXT:    ld1h { z1.d }, p0/z, [x0, x9, lsl #1]
; CHECK-NEXT:    ld1h { z2.d }, p0/z, [x0, x10, lsl #1]
; CHECK-NEXT:    ld1h { z3.d }, p0/z, [x0]
; CHECK-NEXT:    fcvt z0.d, p0/m, z0.h
; CHECK-NEXT:    fcvt z1.d, p0/m, z1.h
; CHECK-NEXT:    stp q0, q1, [x1, #32]
; CHECK-NEXT:    movprfx z0, z3
; CHECK-NEXT:    fcvt z0.d, p0/m, z3.h
; CHECK-NEXT:    movprfx z1, z2
; CHECK-NEXT:    fcvt z1.d, p0/m, z2.h
; CHECK-NEXT:    stp q0, q1, [x1]
; CHECK-NEXT:    ret
  %op1 = load <8 x half>, ptr %a
  %res = fpext <8 x half> %op1 to <8 x double>
  store <8 x double> %res, ptr %b
  ret void
}

define void @fcvt_v16f16_v16f64(ptr %a, ptr %b) #0 {
; CHECK-LABEL: fcvt_v16f16_v16f64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mov x9, #14
; CHECK-NEXT:    mov x10, #12
; CHECK-NEXT:    ptrue p0.d, vl2
; CHECK-NEXT:    mov x8, #2
; CHECK-NEXT:    mov x11, #6
; CHECK-NEXT:    mov x12, #4
; CHECK-NEXT:    ld1h { z0.d }, p0/z, [x0, x9, lsl #1]
; CHECK-NEXT:    ld1h { z1.d }, p0/z, [x0, x10, lsl #1]
; CHECK-NEXT:    mov x9, #8
; CHECK-NEXT:    mov x10, #10
; CHECK-NEXT:    ld1h { z2.d }, p0/z, [x0, x8, lsl #1]
; CHECK-NEXT:    ld1h { z3.d }, p0/z, [x0, x11, lsl #1]
; CHECK-NEXT:    ld1h { z5.d }, p0/z, [x0, x12, lsl #1]
; CHECK-NEXT:    fcvt z0.d, p0/m, z0.h
; CHECK-NEXT:    fcvt z1.d, p0/m, z1.h
; CHECK-NEXT:    ld1h { z4.d }, p0/z, [x0, x9, lsl #1]
; CHECK-NEXT:    ld1h { z6.d }, p0/z, [x0, x10, lsl #1]
; CHECK-NEXT:    ld1h { z7.d }, p0/z, [x0]
; CHECK-NEXT:    stp q1, q0, [x1, #96]
; CHECK-NEXT:    movprfx z1, z4
; CHECK-NEXT:    fcvt z1.d, p0/m, z4.h
; CHECK-NEXT:    movprfx z0, z6
; CHECK-NEXT:    fcvt z0.d, p0/m, z6.h
; CHECK-NEXT:    stp q1, q0, [x1, #64]
; CHECK-NEXT:    movprfx z1, z5
; CHECK-NEXT:    fcvt z1.d, p0/m, z5.h
; CHECK-NEXT:    movprfx z0, z3
; CHECK-NEXT:    fcvt z0.d, p0/m, z3.h
; CHECK-NEXT:    stp q1, q0, [x1, #32]
; CHECK-NEXT:    movprfx z1, z7
; CHECK-NEXT:    fcvt z1.d, p0/m, z7.h
; CHECK-NEXT:    movprfx z0, z2
; CHECK-NEXT:    fcvt z0.d, p0/m, z2.h
; CHECK-NEXT:    stp q1, q0, [x1]
; CHECK-NEXT:    ret
  %op1 = load <16 x half>, ptr %a
  %res = fpext <16 x half> %op1 to <16 x double>
  store <16 x double> %res, ptr %b
  ret void
}

;
; FCVT S -> D
;

define void @fcvt_v1f32_v1f64(ptr %a, ptr %b) #0 {
; CHECK-LABEL: fcvt_v1f32_v1f64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr s0, [x0]
; CHECK-NEXT:    fcvt d0, s0
; CHECK-NEXT:    str d0, [x1]
; CHECK-NEXT:    ret
  %op1 = load <1 x float>, ptr %a
  %res = fpext <1 x float> %op1 to <1 x double>
  store <1 x double> %res, ptr %b
  ret void
}

define void @fcvt_v2f32_v2f64(ptr %a, ptr %b) #0 {
; CHECK-LABEL: fcvt_v2f32_v2f64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ptrue p0.d, vl2
; CHECK-NEXT:    ld1w { z0.d }, p0/z, [x0]
; CHECK-NEXT:    fcvt z0.d, p0/m, z0.s
; CHECK-NEXT:    str q0, [x1]
; CHECK-NEXT:    ret
  %op1 = load <2 x float>, ptr %a
  %res = fpext <2 x float> %op1 to <2 x double>
  store <2 x double> %res, ptr %b
  ret void
}

define void @fcvt_v4f32_v4f64(ptr %a, ptr %b) #0 {
; CHECK-LABEL: fcvt_v4f32_v4f64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mov x8, #2
; CHECK-NEXT:    ptrue p0.d, vl2
; CHECK-NEXT:    ld1w { z0.d }, p0/z, [x0, x8, lsl #2]
; CHECK-NEXT:    ld1w { z1.d }, p0/z, [x0]
; CHECK-NEXT:    fcvt z0.d, p0/m, z0.s
; CHECK-NEXT:    fcvt z1.d, p0/m, z1.s
; CHECK-NEXT:    stp q1, q0, [x1]
; CHECK-NEXT:    ret
  %op1 = load <4 x float>, ptr %a
  %res = fpext <4 x float> %op1 to <4 x double>
  store <4 x double> %res, ptr %b
  ret void
}

define void @fcvt_v8f32_v8f64(ptr %a, ptr %b) #0 {
; CHECK-LABEL: fcvt_v8f32_v8f64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mov x8, #4
; CHECK-NEXT:    mov x9, #6
; CHECK-NEXT:    ptrue p0.d, vl2
; CHECK-NEXT:    mov x10, #2
; CHECK-NEXT:    ld1w { z0.d }, p0/z, [x0, x8, lsl #2]
; CHECK-NEXT:    ld1w { z1.d }, p0/z, [x0, x9, lsl #2]
; CHECK-NEXT:    ld1w { z2.d }, p0/z, [x0, x10, lsl #2]
; CHECK-NEXT:    ld1w { z3.d }, p0/z, [x0]
; CHECK-NEXT:    fcvt z0.d, p0/m, z0.s
; CHECK-NEXT:    fcvt z1.d, p0/m, z1.s
; CHECK-NEXT:    stp q0, q1, [x1, #32]
; CHECK-NEXT:    movprfx z0, z3
; CHECK-NEXT:    fcvt z0.d, p0/m, z3.s
; CHECK-NEXT:    movprfx z1, z2
; CHECK-NEXT:    fcvt z1.d, p0/m, z2.s
; CHECK-NEXT:    stp q0, q1, [x1]
; CHECK-NEXT:    ret
  %op1 = load <8 x float>, ptr %a
  %res = fpext <8 x float> %op1 to <8 x double>
  store <8 x double> %res, ptr %b
  ret void
}

;
; FCVT S -> H
;

define void @fcvt_v2f32_v2f16(ptr %a, ptr %b) #0 {
; CHECK-LABEL: fcvt_v2f32_v2f16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr d0, [x0]
; CHECK-NEXT:    ptrue p0.s, vl2
; CHECK-NEXT:    fcvt z0.h, p0/m, z0.s
; CHECK-NEXT:    st1h { z0.s }, p0, [x1]
; CHECK-NEXT:    ret
  %op1 = load <2 x float>, ptr %a
  %res = fptrunc <2 x float> %op1 to <2 x half>
  store <2 x half> %res, ptr %b
  ret void
}

define void @fcvt_v4f32_v4f16(ptr %a, ptr %b) #0 {
; CHECK-LABEL: fcvt_v4f32_v4f16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr q0, [x0]
; CHECK-NEXT:    ptrue p0.s, vl4
; CHECK-NEXT:    fcvt z0.h, p0/m, z0.s
; CHECK-NEXT:    st1h { z0.s }, p0, [x1]
; CHECK-NEXT:    ret
  %op1 = load <4 x float>, ptr %a
  %res = fptrunc <4 x float> %op1 to <4 x half>
  store <4 x half> %res, ptr %b
  ret void
}

define void @fcvt_v8f32_v8f16(ptr %a, ptr %b) #0 {
; CHECK-LABEL: fcvt_v8f32_v8f16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldp q0, q1, [x0]
; CHECK-NEXT:    mov x8, #4
; CHECK-NEXT:    ptrue p0.s, vl4
; CHECK-NEXT:    fcvt z0.h, p0/m, z0.s
; CHECK-NEXT:    st1h { z0.s }, p0, [x1]
; CHECK-NEXT:    fcvt z1.h, p0/m, z1.s
; CHECK-NEXT:    st1h { z1.s }, p0, [x1, x8, lsl #1]
; CHECK-NEXT:    ret
  %op1 = load <8 x float>, ptr %a
  %res = fptrunc <8 x float> %op1 to <8 x half>
  store <8 x half> %res, ptr %b
  ret void
}

;
; FCVT D -> H
;

define void @fcvt_v1f64_v1f16(ptr %a, ptr %b) #0 {
; CHECK-LABEL: fcvt_v1f64_v1f16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr d0, [x0]
; CHECK-NEXT:    ptrue p0.d, vl1
; CHECK-NEXT:    fcvt z0.h, p0/m, z0.d
; CHECK-NEXT:    st1h { z0.d }, p0, [x1]
; CHECK-NEXT:    ret
  %op1 = load <1 x double>, ptr %a
  %res = fptrunc <1 x double> %op1 to <1 x half>
  store <1 x half> %res, ptr %b
  ret void
}

define void @fcvt_v2f64_v2f16(ptr %a, ptr %b) #0 {
; CHECK-LABEL: fcvt_v2f64_v2f16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr q0, [x0]
; CHECK-NEXT:    ptrue p0.d, vl2
; CHECK-NEXT:    fcvt z0.h, p0/m, z0.d
; CHECK-NEXT:    st1h { z0.d }, p0, [x1]
; CHECK-NEXT:    ret
  %op1 = load <2 x double>, ptr %a
  %res = fptrunc <2 x double> %op1 to <2 x half>
  store <2 x half> %res, ptr %b
  ret void
}

define void @fcvt_v4f64_v4f16(ptr %a, ptr %b) #0 {
; CHECK-LABEL: fcvt_v4f64_v4f16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldp q0, q1, [x0]
; CHECK-NEXT:    mov x8, #2
; CHECK-NEXT:    ptrue p0.d, vl2
; CHECK-NEXT:    fcvt z0.h, p0/m, z0.d
; CHECK-NEXT:    st1h { z0.d }, p0, [x1]
; CHECK-NEXT:    fcvt z1.h, p0/m, z1.d
; CHECK-NEXT:    st1h { z1.d }, p0, [x1, x8, lsl #1]
; CHECK-NEXT:    ret
  %op1 = load <4 x double>, ptr %a
  %res = fptrunc <4 x double> %op1 to <4 x half>
  store <4 x half> %res, ptr %b
  ret void
}

;
; FCVT D -> S
;

define void @fcvt_v1f64_v1f32(<1 x double> %op1, ptr %b) #0 {
; CHECK-LABEL: fcvt_v1f64_v1f32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
; CHECK-NEXT:    ptrue p0.d, vl1
; CHECK-NEXT:    fcvt z0.s, p0/m, z0.d
; CHECK-NEXT:    st1w { z0.d }, p0, [x0]
; CHECK-NEXT:    ret
  %res = fptrunc <1 x double> %op1 to <1 x float>
  store <1 x float> %res, ptr %b
  ret void
}

define void @fcvt_v2f64_v2f32(<2 x double> %op1, ptr %b) #0 {
; CHECK-LABEL: fcvt_v2f64_v2f32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
; CHECK-NEXT:    ptrue p0.d, vl2
; CHECK-NEXT:    fcvt z0.s, p0/m, z0.d
; CHECK-NEXT:    st1w { z0.d }, p0, [x0]
; CHECK-NEXT:    ret
  %res = fptrunc <2 x double> %op1 to <2 x float>
  store <2 x float> %res, ptr %b
  ret void
}

define void @fcvt_v4f64_v4f32(ptr %a, ptr %b) #0 {
; CHECK-LABEL: fcvt_v4f64_v4f32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldp q0, q1, [x0]
; CHECK-NEXT:    mov x8, #2
; CHECK-NEXT:    ptrue p0.d, vl2
; CHECK-NEXT:    fcvt z0.s, p0/m, z0.d
; CHECK-NEXT:    st1w { z0.d }, p0, [x1]
; CHECK-NEXT:    fcvt z1.s, p0/m, z1.d
; CHECK-NEXT:    st1w { z1.d }, p0, [x1, x8, lsl #2]
; CHECK-NEXT:    ret
  %op1 = load <4 x double>, ptr %a
  %res = fptrunc <4 x double> %op1 to <4 x float>
  store <4 x float> %res, ptr %b
  ret void
}

attributes #0 = { "target-features"="+sve" }
